39 #include <px4_platform_common/getopt.h> 40 #include <px4_platform_common/px4_work_queue/ScheduledWorkItem.hpp> 46 #if defined(PX4_I2C_OBDEV_MPU9250) || defined(PX4_I2C_BUS_EXPANSION) 52 #define MPUREG_WHOAMI 0x75 53 #define MPUREG_SMPLRT_DIV 0x19 54 #define MPUREG_CONFIG 0x1A 55 #define MPUREG_GYRO_CONFIG 0x1B 56 #define MPUREG_ACCEL_CONFIG 0x1C 57 #define MPUREG_ACCEL_CONFIG2 0x1D 58 #define MPUREG_LPACCEL_ODR 0x1E 59 #define MPUREG_WOM_THRESH 0x1F 60 #define MPUREG_FIFO_EN 0x23 61 #define MPUREG_I2C_MST_CTRL 0x24 62 #define MPUREG_I2C_SLV0_ADDR 0x25 63 #define MPUREG_I2C_SLV0_REG 0x26 64 #define MPUREG_I2C_SLV0_CTRL 0x27 65 #define MPUREG_I2C_SLV1_ADDR 0x28 66 #define MPUREG_I2C_SLV1_REG 0x29 67 #define MPUREG_I2C_SLV1_CTRL 0x2A 68 #define MPUREG_I2C_SLV2_ADDR 0x2B 69 #define MPUREG_I2C_SLV2_REG 0x2C 70 #define MPUREG_I2C_SLV2_CTRL 0x2D 71 #define MPUREG_I2C_SLV3_ADDR 0x2E 72 #define MPUREG_I2C_SLV3_REG 0x2F 73 #define MPUREG_I2C_SLV3_CTRL 0x30 74 #define MPUREG_I2C_SLV4_ADDR 0x31 75 #define MPUREG_I2C_SLV4_REG 0x32 76 #define MPUREG_I2C_SLV4_DO 0x33 77 #define MPUREG_I2C_SLV4_CTRL 0x34 78 #define MPUREG_I2C_SLV4_DI 0x35 79 #define MPUREG_I2C_MST_STATUS 0x36 80 #define MPUREG_INT_PIN_CFG 0x37 81 #define MPUREG_INT_ENABLE 0x38 82 #define MPUREG_INT_STATUS 0x3A 83 #define MPUREG_ACCEL_XOUT_H 0x3B 84 #define MPUREG_ACCEL_XOUT_L 0x3C 85 #define MPUREG_ACCEL_YOUT_H 0x3D 86 #define MPUREG_ACCEL_YOUT_L 0x3E 87 #define MPUREG_ACCEL_ZOUT_H 0x3F 88 #define MPUREG_ACCEL_ZOUT_L 0x40 89 #define MPUREG_TEMP_OUT_H 0x41 90 #define MPUREG_TEMP_OUT_L 0x42 91 #define MPUREG_GYRO_XOUT_H 0x43 92 #define MPUREG_GYRO_XOUT_L 0x44 93 #define MPUREG_GYRO_YOUT_H 0x45 94 #define MPUREG_GYRO_YOUT_L 0x46 95 #define MPUREG_GYRO_ZOUT_H 0x47 96 #define MPUREG_GYRO_ZOUT_L 0x48 97 #define MPUREG_EXT_SENS_DATA_00 0x49 98 #define MPUREG_I2C_SLV0_D0 0x63 99 #define MPUREG_I2C_SLV1_D0 0x64 100 #define MPUREG_I2C_SLV2_D0 0x65 101 #define MPUREG_I2C_SLV3_D0 0x66 102 #define MPUREG_I2C_MST_DELAY_CTRL 0x67 103 #define MPUREG_SIGNAL_PATH_RESET 0x68 104 #define MPUREG_MOT_DETECT_CTRL 0x69 105 #define MPUREG_USER_CTRL 0x6A 106 #define MPUREG_PWR_MGMT_1 0x6B 107 #define MPUREG_PWR_MGMT_2 0x6C 108 #define MPUREG_FIFO_COUNTH 0x72 109 #define MPUREG_FIFO_COUNTL 0x73 110 #define MPUREG_FIFO_R_W 0x74 113 #define BIT_SLEEP 0x40 114 #define BIT_H_RESET 0x80 115 #define MPU_CLK_SEL_AUTO 0x01 117 #define BITS_GYRO_ST_X 0x80 118 #define BITS_GYRO_ST_Y 0x40 119 #define BITS_GYRO_ST_Z 0x20 120 #define BITS_FS_250DPS 0x00 121 #define BITS_FS_500DPS 0x08 122 #define BITS_FS_1000DPS 0x10 123 #define BITS_FS_2000DPS 0x18 124 #define BITS_FS_MASK 0x18 126 #define BITS_DLPF_CFG_250HZ 0x00 127 #define BITS_DLPF_CFG_184HZ 0x01 128 #define BITS_DLPF_CFG_92HZ 0x02 129 #define BITS_DLPF_CFG_41HZ 0x03 130 #define BITS_DLPF_CFG_20HZ 0x04 131 #define BITS_DLPF_CFG_10HZ 0x05 132 #define BITS_DLPF_CFG_5HZ 0x06 133 #define BITS_DLPF_CFG_3600HZ 0x07 134 #define BITS_DLPF_CFG_MASK 0x07 136 #define BITS_ACCEL_CONFIG2_41HZ 0x03 138 #define BIT_RAW_RDY_EN 0x01 139 #define BIT_INT_ANYRD_2CLEAR 0x10 140 #define BIT_INT_BYPASS_EN 0x02 142 #define BIT_I2C_READ_FLAG 0x80 144 #define BIT_I2C_SLV0_NACK 0x01 145 #define BIT_I2C_FIFO_EN 0x40 146 #define BIT_I2C_MST_EN 0x20 147 #define BIT_I2C_IF_DIS 0x10 148 #define BIT_FIFO_RST 0x04 149 #define BIT_I2C_MST_RST 0x02 150 #define BIT_SIG_COND_RST 0x01 152 #define BIT_I2C_SLV0_EN 0x80 153 #define BIT_I2C_SLV0_BYTE_SW 0x40 154 #define BIT_I2C_SLV0_REG_DIS 0x20 155 #define BIT_I2C_SLV0_REG_GRP 0x10 157 #define BIT_I2C_MST_MULT_MST_EN 0x80 158 #define BIT_I2C_MST_WAIT_FOR_ES 0x40 159 #define BIT_I2C_MST_SLV_3_FIFO_EN 0x20 160 #define BIT_I2C_MST_P_NSR 0x10 161 #define BITS_I2C_MST_CLOCK_258HZ 0x08 162 #define BITS_I2C_MST_CLOCK_400HZ 0x0D 164 #define BIT_I2C_SLV0_DLY_EN 0x01 165 #define BIT_I2C_SLV1_DLY_EN 0x02 166 #define BIT_I2C_SLV2_DLY_EN 0x04 167 #define BIT_I2C_SLV3_DLY_EN 0x08 169 #define MPU_WHOAMI_9250 0x71 170 #define MPU_WHOAMI_6500 0x70 172 #define MPU9250_ACCEL_DEFAULT_RATE 1000 173 #define MPU9250_ACCEL_MAX_OUTPUT_RATE 280 174 #define MPU9250_ACCEL_DEFAULT_DRIVER_FILTER_FREQ 30 175 #define MPU9250_GYRO_DEFAULT_RATE 1000 177 #define MPU9250_GYRO_MAX_OUTPUT_RATE MPU9250_ACCEL_MAX_OUTPUT_RATE 178 #define MPU9250_GYRO_DEFAULT_DRIVER_FILTER_FREQ 30 180 #define MPU9250_DEFAULT_ONCHIP_FILTER_FREQ 92 182 #pragma pack(push, 1) 208 #define MPU9250_LOW_BUS_SPEED 0 209 #define MPU9250_HIGH_BUS_SPEED 0x8000 210 #define MPU9250_REG_MASK 0x00FF 211 # define MPU9250_IS_HIGH_SPEED(r) ((r) & MPU9250_HIGH_BUS_SPEED) 212 # define MPU9250_REG(r) ((r) & MPU9250_REG_MASK) 213 # define MPU9250_SET_SPEED(r, s) ((r)|(s)) 214 # define MPU9250_HIGH_SPEED_OP(r) MPU9250_SET_SPEED((r), MPU9250_HIGH_BUS_SPEED) 215 # define MPU9250_LOW_SPEED_OP(r) ((r) &~MPU9250_HIGH_BUS_SPEED) 257 unsigned _call_interval{1000};
259 unsigned _dlpf_freq{0};
261 unsigned _sample_rate{1000};
269 uint8_t _register_wait{0};
270 uint64_t _reset_wait{0};
276 static constexpr
int MPU9250_NUM_CHECKED_REGISTERS{11};
277 static const uint16_t _mpu9250_checked_registers[MPU9250_NUM_CHECKED_REGISTERS];
281 uint8_t _checked_values[MPU9250_NUM_CHECKED_REGISTERS] {};
282 uint8_t _checked_bad[MPU9250_NUM_CHECKED_REGISTERS] {};
283 unsigned _checked_next{0};
284 unsigned _num_checked_registers{0};
288 float _last_temperature{0.0f};
290 bool check_null_data(uint16_t *
data, uint8_t size);
291 bool check_duplicate(uint8_t *accel_data);
294 uint8_t _last_accel_data[6] {};
295 bool _got_duplicate{
false};
319 uint16_t read_reg16(
unsigned reg);
331 uint8_t read_reg_range(
unsigned start_reg, uint32_t speed, uint8_t *buf, uint16_t count);
339 void write_reg(
unsigned reg, uint8_t value);
350 void modify_reg(
unsigned reg, uint8_t clearbits, uint8_t setbits);
358 void write_checked_reg(
unsigned reg, uint8_t value);
369 void modify_checked_reg(
unsigned reg, uint8_t clearbits, uint8_t setbits);
377 int set_accel_range(
unsigned max_g);
382 uint16_t
swap16(uint16_t val) {
return (val >> 8) | (val << 8); }
394 void _set_dlpf_filter(uint16_t frequency_hz);
399 void _set_sample_rate(
unsigned desired_sample_rate_hz);
404 void check_registers();
perf_counter_t _good_transfers
Definition of geo / math functions to perform geodesic calculations.
device::Device * _interface
void write_reg(unsigned reg, uint8_t value)
A set of useful macros for enhanced runtime and compile time error detection and warning suppression...
int reset(enum LPS22HB_BUS busid)
Reset the driver.
device::Device * MPU9250_I2C_interface(int bus, uint32_t address)
device::Device * MPU9250_SPI_interface(int bus, uint32_t cs)
Report conversation within the mpu, including command byte and interrupt status.
void init()
Activates/configures the hardware registers.
Definition of commonly used conversions.
perf_counter_t _bad_transfers
Rotation
Enum for board and external compass rotations.
uint8_t read_reg(unsigned reg)
uint16_t swap16(uint16_t val)
Swap a 16-bit value read from the mpu to native byte order.
int MPU9250_probe(device::Device *dev)
Helper class implementing the magnetometer driver node.
#define MPU9250_LOW_BUS_SPEED
virtual bool external() const
perf_counter_t _duplicates
perf_counter_t _bad_registers
Fundamental base class for all physical drivers (I2C, SPI).
bool is_external()
Get the internal / external state.
PX4Accelerometer _px4_accel
perf_counter_t _sample_perf
static constexpr uint8_t _checked_registers[]