PX4 Firmware
PX4 Autopilot Software http://px4.io
flexcan.hpp
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2018 Pavel Kirienko <pavel.kirienko@gmail.com>
3  * Kinetis Port Author David Sidrane <david_s5@nscdg.com>
4  * Bit definitions were copied from NuttX KINETIS CAN driver.
5  */
6 
7 #pragma once
8 
10 
11 #include <uavcan/uavcan.hpp>
12 #include <stdint.h>
13 
14 #ifndef UAVCAN_CPP_VERSION
15 # error UAVCAN_CPP_VERSION
16 #endif
17 
18 #if UAVCAN_CPP_VERSION < UAVCAN_CPP11
19 // #undef'ed at the end of this file
20 # define constexpr const
21 #endif
22 
23 namespace uavcan_kinetis
24 {
25 namespace flexcan
26 {
27 enum { HWMaxMB = 16 };
28 
29 union MBcsType {
30  volatile uint32_t w;
31  struct {
32  volatile uint32_t time_stamp : 16;
33  volatile uint32_t dlc : 4;
34  volatile uint32_t rtr : 1;
35  volatile uint32_t ide : 1;
36  volatile uint32_t srr : 1;
37  volatile uint32_t res : 1;
38  volatile uint32_t code : 4;
39  volatile uint32_t res2 : 4;
40  };
41 };
42 
43 union FIFOcsType {
44  volatile uint32_t cs;
45  struct {
46  volatile uint32_t time_stamp : 16;
47  volatile uint32_t dlc : 4;
48  volatile uint32_t rtr : 1;
49  volatile uint32_t ide : 1;
50  volatile uint32_t srr : 1;
51  volatile uint32_t res : 9;
52  };
53 };
54 
55 union IDType {
56  volatile uint32_t w;
57  struct {
58  volatile uint32_t ext : 29;
59  volatile uint32_t resex : 3;
60  };
61  struct {
62  volatile uint32_t res : 18;
63  volatile uint32_t std : 11;
64  volatile uint32_t resstd : 3;
65  };
66 };
67 
68 union FilterType {
69  volatile uint32_t w;
70  struct {
71  volatile uint32_t res : 1; // Bit 0 - Reserved
72  volatile uint32_t ext : 29; // Bits 1 - 29 EID
73  };
74  struct {
75  volatile uint32_t ress : 19; // Bits 0, 1-18 Reserved
76  volatile uint32_t std : 11; // StD ID
77  };
78  struct {
79  volatile uint32_t resc : 30; // Bits 0 - 29 Reserved
80  volatile uint32_t ide : 1; // Bit 30 - EID
81  volatile uint32_t rtr : 1; // Bit 31 Remote
82  };
83 };
84 
85 union DataType {
86  volatile uint32_t l;
87  volatile uint32_t h;
88  struct {
89  volatile uint32_t b3 : 8;
90  volatile uint32_t b2 : 8;
91  volatile uint32_t b1 : 8;
92  volatile uint32_t b0 : 8;
93  volatile uint32_t b7 : 8;
94  volatile uint32_t b6 : 8;
95  volatile uint32_t b5 : 8;
96  volatile uint32_t b4 : 8;
97  };
98 };
99 
100 
105 };
106 
108  TxMbInactive = 0x8, /*!< MB is not active.*/
109  TxMbAbort = 0x9, /*!< MB is aborted.*/
110  TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */
111  /*!< MB is a TX Remote Request Frame (when MB RTR = 1).*/
112  TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from */
113  /*! an incoming Remote Request Frame.*/
114  TxMbNotUsed = 0xF, /*!< Not used.*/
115 };
116 
117 struct RxFiFoType {
121 };
122 
124  kRxMbInactive = 0x0, /*!< MB is not active.*/
125  kRxMbFull = 0x2, /*!< MB is full.*/
126  kRxMbEmpty = 0x4, /*!< MB is active and empty.*/
127  kRxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/
128  kRxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/
129  /*! The CPU must not access the MB.*/
130  kRxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */
131  /*! and transmit a Response Frame in return.*/
132  kRxMbNotUsed = 0xF, /*!< Not used.*/
133 };
134 
135 struct CanType {
136  volatile uint32_t MCR; /*!< Module Configuration Register, Address offset: 0x0000 */
137  volatile uint32_t CTRL1; /*!< Control 1 Register, Address offset: 0x0004 */
138  volatile uint32_t TIMER; /*!< Free Running Timer, Address offset: 0x0008 */
139  uint32_t Reserved0; /*!< Reserved Address offset: 0x000c */
140  volatile uint32_t RXMGMASK; /*!< Rx Mailboxes Global Mask Register, Address offset: 0x0010 */
141  volatile uint32_t RX14MASK; /*!< Rx 14 Mask Register, Address offset: 0x0014 */
142  volatile uint32_t RX15MASK; /*!< Rx 15 Mask Register, Address offset: 0x0018 */
143  volatile uint32_t ECR; /*!< Error Counter, Address offset: 0x001c */
144  volatile uint32_t ESR1; /*!< Error and Status 1 Register, Address offset: 0x0020 */
145  uint32_t Reserved1; /*!< Reserved Address offset: 0x0024 */
146  volatile uint32_t IMASK1; /*!< Interrupt Masks 1 Register, Address offset: 0x0028 */
147  uint32_t Reserved2; /*!< Reserved Address offset: 0x002C */
148  volatile uint32_t IFLAG1; /*!< Interrupt Flags 1 Register, Address offset: 0x0030 */
149  volatile uint32_t CTRL2; /*!< Control 2 Register, Address offset: 0x0034 */
150  volatile uint32_t ESR2; /*!< Error and Status 2 Register, Address offset: 0x0038 */
151  uint32_t Reserved3; /*!< Reserved Address offset: 0x003c */
152  uint32_t Reserved4; /*!< Reserved Address offset: 0x0040 */
153  volatile uint32_t CRCR; /*!< CRC Register, Address offset: 0x0044 */
154  volatile uint32_t RXFGMASK; /*!< Rx FIFO Global Mask Register, Address offset: 0x0048 */
155  volatile uint32_t RXFIR; /*!< Rx FIFO Information Register, Address offset: 0x004c */
156  uint32_t RESERVED5[12]; /*!< Reserved Address offset: 0x0050 */
157  union {
160  } MB[HWMaxMB];
161  uint32_t RESERVED6[448]; /*!< Reserved Address offset: 0x0180 */
162  volatile FilterType RXIMR[HWMaxMB]; /*!< R0 Individual Mask Registers, Address offset: 0x0880
163  */
164 };
165 
166 /* Layout of Fifo, filters and Message buffers */
167 
168 enum { FiFo = 0 };
169 /* 0 */
170 /* 1 */
171 /* 2 */
172 /* 3 Fifo */
173 /* 4 */
174 /* 5 */
175 enum { FirstFilter = 6 };
176 /* 6 */
177 /* 7 */
178 /* 8 Filters */
179 /* 9 */
180 enum { NumHWFilters = 16 };
181 enum { NumMBinFiFoAndFilters = 10 };
182 /* 10 */
183 /* 11 */
184 /* 12 */
185 /* 13 Tx Message Buffers */
186 /* 14 */
187 /* 15 */
188 /*-- ----------------------*/
189 
190 enum { TXMBMask = (0b111111 << NumMBinFiFoAndFilters) };
191 
192 /**
193  * CANx register sets
194  */
195 
196 /* Address of the CAN registers */
197 
198 CanType *const Can[UAVCAN_KINETIS_NUM_IFACES] = {
199  reinterpret_cast<CanType *>(0x40024000) // CAN0
200 #if UAVCAN_KINETIS_NUM_IFACES > 1
201  ,
202  reinterpret_cast<CanType *>(0x400A4000) // CAN1
203 #endif
204 };
205 
206 /* Module Configuration Register */
207 
208 constexpr unsigned long MCR_MAXMB_SHIFT = (0); /* Bits 0-6: Number of the Last Message Buffer */
209 constexpr unsigned long MCR_MAXMB_MASK = (0x7fU << MCR_MAXMB_SHIFT);
210 /* Bit 7: Reserved */
211 constexpr unsigned long MCR_IDAM_SHIFT = (8); /* Bits 8-9: ID Acceptance Mode */
212 constexpr unsigned long MCR_IDAM_MASK = (3U << MCR_IDAM_SHIFT);
213 constexpr unsigned long MCR_IDAM_FMTA(0U << MCR_IDAM_SHIFT); /* Format A: One full ID */
214 constexpr unsigned long CAN_MCR_IDAM_FMTB(1U << MCR_IDAM_SHIFT); /* Format B: Two full (or partial) IDs */
215 constexpr unsigned long MCR_IDAM_FMTC(2U << MCR_IDAM_SHIFT); /* Format C: Four partial IDs */
216 constexpr unsigned long MCR_IDAM_FMTD(3U << MCR_IDAM_SHIFT); /* Format D: All frames rejected */
217 /* Bits 10-11: Reserved */
218 constexpr unsigned long MCR_AEN = (1U << 12); /* Bit 12: Abort Enable */
219 constexpr unsigned long MCR_LPRIOEN = (1U << 13); /* Bit 13: Local Priority Enable */
220 /* Bits 14-15: Reserved */
221 constexpr unsigned long MCR_IRMQ = (1U << 16); /* Bit 16: Individual Rx Masking and Queue Enable */
222 constexpr unsigned long MCR_SRXDIS = (1U << 17); /* Bit 17: Self Reception Disable */
223 /* Bit 18: Reserved */
224 constexpr unsigned long MCR_WAKSRC = (1U << 19); /* Bit 19: Wake up Source */
225 constexpr unsigned long MCR_LPMACK = (1U << 20); /* Bit 20: Low Power Mode Acknowledge */
226 constexpr unsigned long MCR_WRNEN = (1U << 21); /* Bit 21: Warning Interrupt Enable */
227 constexpr unsigned long MCR_SLFWAK = (1U << 22); /* Bit 22: Self Wake Up */
228 constexpr unsigned long MCR_SUPV = (1U << 23); /* Bit 23: Supervisor Mode */
229 constexpr unsigned long MCR_FRZACK = (1U << 24); /* Bit 24: Freeze Mode Acknowledge */
230 constexpr unsigned long MCR_SOFTRST = (1U << 25); /* Bit 25: Soft Reset */
231 constexpr unsigned long MCR_WAKMSK = (1U << 26); /* Bit 26: Wake Up Interrupt Mask */
232 constexpr unsigned long MCR_NOTRDY = (1U << 27); /* Bit 27: FlexCAN Not Ready */
233 constexpr unsigned long MCR_HALT = (1U << 28); /* Bit 28: Halt FlexCAN */
234 constexpr unsigned long MCR_RFEN = (1U << 29); /* Bit 29: Rx FIFO Enable */
235 constexpr unsigned long MCR_FRZ = (1U << 30); /* Bit 30: Freeze Enable */
236 constexpr unsigned long MCR_MDIS = (1U << 31); /* Bit 31: Module Disable */
237 
238 /* Control 1 Register */
239 
240 constexpr unsigned long CTRL1_ROPSEG_SHIFT = (0); /* Bits 0-2: Propagation Segment */
241 constexpr unsigned long CTRL1_ROPSEG_MASK = (7U << CTRL1_ROPSEG_SHIFT);
242 constexpr unsigned long CTRL1_LOM = (1U << 3); /* Bit 3: Listen-Only Mode */
243 constexpr unsigned long CTRL1_LBUF = (1U << 4); /* Bit 4: Lowest Buffer Transmitted First */
244 constexpr unsigned long CTRL1_TSYN = (1U << 5); /* Bit 5: Timer Sync */
245 constexpr unsigned long CTRL1_BOFFREC = (1U << 6); /* Bit 6: Bus Off Recovery */
246 constexpr unsigned long CTRL1_SMP = (1U << 7); /* Bit 7: CAN Bit Sampling */
247 /* Bits 8-9: Reserved */
248 constexpr unsigned long CTRL1_RWRNMSK = (1U << 10); /* Bit 10: Rx Warning Interrupt Mask */
249 constexpr unsigned long CTRL1_TWRNMSK = (1U << 11); /* Bit 11: Tx Warning Interrupt Mask */
250 constexpr unsigned long CTRL1_LPB = (1U << 12); /* Bit 12: Loop Back Mode */
251 constexpr unsigned long CTRL1_CLKSRC = (1U << 13); /* Bit 13: CAN Engine Clock Source */
252 constexpr unsigned long CTRL1_ERRMSK = (1U << 14); /* Bit 14: Error Mask */
253 constexpr unsigned long CTRL1_BOFFMSK = (1U << 15); /* Bit 15: Bus Off Mask */
254 constexpr unsigned long CTRL1_PSEG2_SHIFT = (16); /* Bits 16-18: Phase Segment 2 */
255 constexpr unsigned long CTRL1_PSEG2_MASK = (7U << CTRL1_PSEG2_SHIFT);
256 constexpr unsigned long CTRL1_PSEG1_SHIFT = (19); /* Bits 19-21: Phase Segment 1 */
257 constexpr unsigned long CTRL1_PSEG1_MASK = (7U << CTRL1_PSEG1_SHIFT);
258 constexpr unsigned long CTRL1_RJW_SHIFT = (22); /* Bits 22-23: Resync Jump Width */
259 constexpr unsigned long CTRL1_RJW_MASK = (3U << CTRL1_RJW_SHIFT);
260 constexpr unsigned long CTRL1_PRESDIV_SHIFT = (24); /* Bits 24-31: Prescaler Division Factor */
261 constexpr unsigned long CTRL1_PRESDIV_MASK = (0xff << CTRL1_PRESDIV_SHIFT);
262 
263 /* Free Running Timer */
264 
265 constexpr unsigned long TIMER_SHIFT = (0U); /* Bits 0-15: Timer value */
266 constexpr unsigned long TIMER_MASK = (0xffffU << TIMER_SHIFT);
267 /* Bits 16-31: Reserved */
268 /* Rx Mailboxes Global Mask Register (32 Rx Mailboxes Global Mask Bits) */
269 
270 constexpr unsigned long RXMGMASK0 = (1U << 0); /* Bit 0: Rx Mailbox 0 Global Mask Bit */
271 constexpr unsigned long RXMGMASK1 = (1U << 1); /* Bit 1: Rx Mailbox 1 Global Mask Bit */
272 constexpr unsigned long RXMGMASK2 = (1U << 2); /* Bit 2: Rx Mailbox 2 Global Mask Bit */
273 constexpr unsigned long RXMGMASK3 = (1U << 3); /* Bit 3: Rx Mailbox 3 Global Mask Bit */
274 constexpr unsigned long RXMGMASK4 = (1U << 4); /* Bit 4: Rx Mailbox 4 Global Mask Bit */
275 constexpr unsigned long RXMGMASK5 = (1U << 5); /* Bit 5: Rx Mailbox 5 Global Mask Bit */
276 constexpr unsigned long RXMGMASK6 = (1U << 6); /* Bit 6: Rx Mailbox 6 Global Mask Bit */
277 constexpr unsigned long RXMGMASK7 = (1U << 7); /* Bit 7: Rx Mailbox 7 Global Mask Bit */
278 constexpr unsigned long RXMGMASK8 = (1U << 8); /* Bit 8: Rx Mailbox 8 Global Mask Bit */
279 constexpr unsigned long RXMGMASK9 = (1U << 9); /* Bit 9: Rx Mailbox 9 Global Mask Bit */
280 constexpr unsigned long RXMGMASK10 = (1U << 10); /* Bit 10: Rx Mailbox 10 Global Mask Bit */
281 constexpr unsigned long RXMGMASK11 = (1U << 11); /* Bit 11: Rx Mailbox 11 Global Mask Bit */
282 constexpr unsigned long RXMGMASK12 = (1U << 12); /* Bit 12: Rx Mailbox 12 Global Mask Bit */
283 constexpr unsigned long RXMGMASK13 = (1U << 13); /* Bit 13: Rx Mailbox 13 Global Mask Bit */
284 constexpr unsigned long RXMGMASK14 = (1U << 14); /* Bit 14: Rx Mailbox 14 Global Mask Bit */
285 constexpr unsigned long RXMGMASK15 = (1U << 15); /* Bit 15: Rx Mailbox 15 Global Mask Bit */
286 constexpr unsigned long RXMGMASK16 = (1U << 16); /* Bit 16: Rx Mailbox 16 Global Mask Bit */
287 constexpr unsigned long RXMGMASK17 = (1U << 17); /* Bit 17: Rx Mailbox 17 Global Mask Bit */
288 constexpr unsigned long RXMGMASK18 = (1U << 18); /* Bit 18: Rx Mailbox 18 Global Mask Bit */
289 constexpr unsigned long RXMGMASK19 = (1U << 19); /* Bit 19: Rx Mailbox 19 Global Mask Bit */
290 constexpr unsigned long RXMGMASK20 = (1U << 20); /* Bit 20: Rx Mailbox 20 Global Mask Bit */
291 constexpr unsigned long RXMGMASK21 = (1U << 21); /* Bit 21: Rx Mailbox 21 Global Mask Bit */
292 constexpr unsigned long RXMGMASK22 = (1U << 22); /* Bit 22: Rx Mailbox 22 Global Mask Bit */
293 constexpr unsigned long RXMGMASK23 = (1U << 23); /* Bit 23: Rx Mailbox 23 Global Mask Bit */
294 constexpr unsigned long RXMGMASK24 = (1U << 24); /* Bit 24: Rx Mailbox 24 Global Mask Bit */
295 constexpr unsigned long RXMGMASK25 = (1U << 25); /* Bit 25: Rx Mailbox 25 Global Mask Bit */
296 constexpr unsigned long RXMGMASK26 = (1U << 26); /* Bit 26: Rx Mailbox 26 Global Mask Bit */
297 constexpr unsigned long RXMGMASK27 = (1U << 27); /* Bit 27: Rx Mailbox 27 Global Mask Bit */
298 constexpr unsigned long RXMGMASK28 = (1U << 28); /* Bit 28: Rx Mailbox 28 Global Mask Bit */
299 constexpr unsigned long RXMGMASK29 = (1U << 29); /* Bit 29: Rx Mailbox 29 Global Mask Bit */
300 constexpr unsigned long RXMGMASK30 = (1U << 30); /* Bit 30: Rx Mailbox 30 Global Mask Bit */
301 constexpr unsigned long RXMGMASK31 = (1U << 31); /* Bit 31: Rx Mailbox 31 Global Mask Bit */
302 
303 /* Rx 14 Mask Register */
304 
305 constexpr unsigned long RXM14MASK0 = (1U << 0); /* Bit 0: Rx Buffer 14 Mask Bit 0 */
306 constexpr unsigned long RXM14MASK1 = (1U << 1); /* Bit 1: Rx Buffer 14 Mask Bit 1 */
307 constexpr unsigned long RXM14MASK2 = (1U << 2); /* Bit 2: Rx Buffer 14 Mask Bit 2 */
308 constexpr unsigned long RXM14MASK3 = (1U << 3); /* Bit 3: Rx Buffer 14 Mask Bit 3 */
309 constexpr unsigned long RXM14MASK4 = (1U << 4); /* Bit 4: Rx Buffer 14 Mask Bit 4 */
310 constexpr unsigned long RXM14MASK5 = (1U << 5); /* Bit 5: Rx Buffer 14 Mask Bit 5 */
311 constexpr unsigned long RXM14MASK6 = (1U << 6); /* Bit 6: Rx Buffer 14 Mask Bit 6 */
312 constexpr unsigned long RXM14MASK7 = (1U << 7); /* Bit 7: Rx Buffer 14 Mask Bit 7 */
313 constexpr unsigned long RXM14MASK8 = (1U << 8); /* Bit 8: Rx Buffer 14 Mask Bit 8 */
314 constexpr unsigned long RXM14MASK9 = (1U << 9); /* Bit 9: Rx Buffer 14 Mask Bit 9 */
315 constexpr unsigned long RXM14MASK10 = (1U << 10); /* Bit 10: Rx Buffer 14 Mask Bit 10 */
316 constexpr unsigned long RXM14MASK11 = (1U << 11); /* Bit 11: Rx Buffer 14 Mask Bit 11 */
317 constexpr unsigned long RXM14MASK12 = (1U << 12); /* Bit 12: Rx Buffer 14 Mask Bit 12 */
318 constexpr unsigned long RXM14MASK13 = (1U << 13); /* Bit 13: Rx Buffer 14 Mask Bit 13 */
319 constexpr unsigned long RXM14MASK14 = (1U << 14); /* Bit 14: Rx Buffer 14 Mask Bit 14 */
320 constexpr unsigned long RXM14MASK15 = (1U << 15); /* Bit 15: Rx Buffer 14 Mask Bit 15 */
321 constexpr unsigned long RXM14MASK16 = (1U << 16); /* Bit 16: Rx Buffer 14 Mask Bit 16 */
322 constexpr unsigned long RXM14MASK17 = (1U << 17); /* Bit 17: Rx Buffer 14 Mask Bit 17 */
323 constexpr unsigned long RXM14MASK18 = (1U << 18); /* Bit 18: Rx Buffer 14 Mask Bit 18 */
324 constexpr unsigned long RXM14MASK19 = (1U << 19); /* Bit 19: Rx Buffer 14 Mask Bit 19 */
325 constexpr unsigned long RXM14MASK20 = (1U << 20); /* Bit 20: Rx Buffer 14 Mask Bit 20 */
326 constexpr unsigned long RXM14MASK21 = (1U << 21); /* Bit 21: Rx Buffer 14 Mask Bit 21 */
327 constexpr unsigned long RXM14MASK22 = (1U << 22); /* Bit 22: Rx Buffer 14 Mask Bit 22 */
328 constexpr unsigned long RXM14MASK23 = (1U << 23); /* Bit 23: Rx Buffer 14 Mask Bit 23 */
329 constexpr unsigned long RXM14MASK24 = (1U << 24); /* Bit 24: Rx Buffer 14 Mask Bit 24 */
330 constexpr unsigned long RXM14MASK25 = (1U << 25); /* Bit 25: Rx Buffer 14 Mask Bit 25 */
331 constexpr unsigned long RXM14MASK26 = (1U << 26); /* Bit 26: Rx Buffer 14 Mask Bit 26 */
332 constexpr unsigned long RXM14MASK27 = (1U << 27); /* Bit 27: Rx Buffer 14 Mask Bit 27 */
333 constexpr unsigned long RXM14MASK28 = (1U << 28); /* Bit 28: Rx Buffer 14 Mask Bit 28 */
334 constexpr unsigned long RXM14MASK29 = (1U << 29); /* Bit 29: Rx Buffer 14 Mask Bit 29 */
335 constexpr unsigned long RXM14MASK30 = (1U << 30); /* Bit 30: Rx Buffer 14 Mask Bit 30 */
336 constexpr unsigned long RXM14MASK31 = (1U << 31); /* Bit 31: Rx Buffer 14 Mask Bit 31 */
337 
338 /* Rx 15 Mask Register */
339 
340 constexpr unsigned long RXM15MASK0 = (1U << 0); /* Bit 0: Rx Buffer 15 Mask Bit 0 */
341 constexpr unsigned long RXM15MASK1 = (1U << 1); /* Bit 1: Rx Buffer 15 Mask Bit 1 */
342 constexpr unsigned long RXM15MASK2 = (1U << 2); /* Bit 2: Rx Buffer 15 Mask Bit 2 */
343 constexpr unsigned long RXM15MASK3 = (1U << 3); /* Bit 3: Rx Buffer 15 Mask Bit 3 */
344 constexpr unsigned long RXM15MASK4 = (1U << 4); /* Bit 4: Rx Buffer 15 Mask Bit 4 */
345 constexpr unsigned long RXM15MASK5 = (1U << 5); /* Bit 5: Rx Buffer 15 Mask Bit 5 */
346 constexpr unsigned long RXM15MASK6 = (1U << 6); /* Bit 6: Rx Buffer 15 Mask Bit 6 */
347 constexpr unsigned long RXM15MASK7 = (1U << 7); /* Bit 7: Rx Buffer 15 Mask Bit 7 */
348 constexpr unsigned long RXM15MASK8 = (1U << 8); /* Bit 8: Rx Buffer 15 Mask Bit 8 */
349 constexpr unsigned long RXM15MASK9 = (1U << 9); /* Bit 9: Rx Buffer 15 Mask Bit 9 */
350 constexpr unsigned long RXM15MASK10 = (1U << 10); /* Bit 10: Rx Buffer 15 Mask Bit 10 */
351 constexpr unsigned long RXM15MASK11 = (1U << 11); /* Bit 11: Rx Buffer 15 Mask Bit 11 */
352 constexpr unsigned long RXM15MASK12 = (1U << 12); /* Bit 12: Rx Buffer 15 Mask Bit 12 */
353 constexpr unsigned long RXM15MASK13 = (1U << 13); /* Bit 13: Rx Buffer 15 Mask Bit 13 */
354 constexpr unsigned long RXM15MASK14 = (1U << 14); /* Bit 14: Rx Buffer 15 Mask Bit 14 */
355 constexpr unsigned long RXM15MASK15 = (1U << 15); /* Bit 15: Rx Buffer 15 Mask Bit 15 */
356 constexpr unsigned long RXM15MASK16 = (1U << 16); /* Bit 16: Rx Buffer 15 Mask Bit 16 */
357 constexpr unsigned long RXM15MASK17 = (1U << 17); /* Bit 17: Rx Buffer 15 Mask Bit 17 */
358 constexpr unsigned long RXM15MASK18 = (1U << 18); /* Bit 18: Rx Buffer 15 Mask Bit 18 */
359 constexpr unsigned long RXM15MASK19 = (1U << 19); /* Bit 19: Rx Buffer 15 Mask Bit 19 */
360 constexpr unsigned long RXM15MASK20 = (1U << 20); /* Bit 20: Rx Buffer 15 Mask Bit 20 */
361 constexpr unsigned long RXM15MASK21 = (1U << 21); /* Bit 21: Rx Buffer 15 Mask Bit 21 */
362 constexpr unsigned long RXM15MASK22 = (1U << 22); /* Bit 22: Rx Buffer 15 Mask Bit 22 */
363 constexpr unsigned long RXM15MASK23 = (1U << 23); /* Bit 23: Rx Buffer 15 Mask Bit 23 */
364 constexpr unsigned long RXM15MASK24 = (1U << 24); /* Bit 24: Rx Buffer 15 Mask Bit 24 */
365 constexpr unsigned long RXM15MASK25 = (1U << 25); /* Bit 25: Rx Buffer 15 Mask Bit 25 */
366 constexpr unsigned long RXM15MASK26 = (1U << 26); /* Bit 26: Rx Buffer 15 Mask Bit 26 */
367 constexpr unsigned long RXM15MASK27 = (1U << 27); /* Bit 27: Rx Buffer 15 Mask Bit 27 */
368 constexpr unsigned long RXM15MASK28 = (1U << 28); /* Bit 28: Rx Buffer 15 Mask Bit 28 */
369 constexpr unsigned long RXM15MASK29 = (1U << 29); /* Bit 29: Rx Buffer 15 Mask Bit 29 */
370 constexpr unsigned long RXM15MASK30 = (1U << 30); /* Bit 30: Rx Buffer 15 Mask Bit 30 */
371 constexpr unsigned long RXM15MASK31 = (1U << 31); /* Bit 31: Rx Buffer 15 Mask Bit 31 */
372 
373 /* Error Counter */
374 
375 constexpr unsigned long ECR_TXERRCNT_SHIFT = (0U); /* Bits 0-7: Transmit Error Counter */
376 constexpr unsigned long ECR_TXERRCNT_MASK = (0xff << ECR_TXERRCNT_SHIFT);
377 constexpr unsigned long ECR_RXERRCNT_SHIFT = (8); /* Bits 8-15: Receive Error Counter */
378 constexpr unsigned long ECR_RXERRCNT_MASK = (0xff << ECR_RXERRCNT_SHIFT);
379 /* Bits 16-31: Reserved */
380 
381 /* Error and Status 1 Register */
382 
383 constexpr unsigned long ESR1_WAKINT = (1U << 0); /* Bit 0: Wake-Up Interrupt */
384 constexpr unsigned long ESR1_ERRINT = (1U << 1); /* Bit 1: Error Interrupt */
385 constexpr unsigned long ESR1_BOFFINT = (1U << 2); /* Bit 2: 'Bus Off' Interrupt */
386 constexpr unsigned long ESR1_RX = (1U << 3); /* Bit 3: FlexCAN in Reception */
387 constexpr unsigned long ESR1_FLTCONF_SHIFT = (4U); /* Bits 4-5: Fault Confinement State */
388 constexpr unsigned long ESR1_FLTCONF_MASK = (3U << ESR1_FLTCONF_SHIFT);
389 constexpr unsigned long ESR1_FLTCONF_ACTV = (0U << ESR1_FLTCONF_SHIFT); /* Error Active */
390 constexpr unsigned long ESR1_FLTCONF_PASV = (1U << ESR1_FLTCONF_SHIFT); /* Error Passive */
391 constexpr unsigned long ESR1_FLTCONF_OFF = (2U << ESR1_FLTCONF_SHIFT); /* Bus Off */
392 constexpr unsigned long ESR1_TX = (1U << 6); /* Bit 6: FlexCAN in Transmission */
393 constexpr unsigned long ESR1_IDLE = (1U << 7); /* Bit 7: CAN bus is in IDLE state */
394 constexpr unsigned long ESR1_RXWRN = (1U << 8); /* Bit 8: Rx Error Warning */
395 constexpr unsigned long ESR1_TXWRN = (1U << 9); /* Bit 9: TX Error Warning */
396 constexpr unsigned long ESR1_STFERR = (1U << 10); /* Bit 10: Stuffing Error */
397 constexpr unsigned long ESR1_FRMERR = (1U << 11); /* Bit 11: Form Error */
398 constexpr unsigned long ESR1_CRCERR = (1U << 12); /* Bit 12: Cyclic Redundancy Check Error */
399 constexpr unsigned long ESR1_ACKERR = (1U << 13); /* Bit 13: Acknowledge Error */
400 constexpr unsigned long ESR1_BIT0ERR = (1U << 14); /* Bit 14: Bit0 Error */
401 constexpr unsigned long ESR1_BIT1ERR = (1U << 15); /* Bit 15: Bit1 Error */
402 constexpr unsigned long ESR1_RWRNINT = (1U << 16); /* Bit 16: Rx Warning Interrupt Flag */
403 constexpr unsigned long ESR1_TWRNINT = (1U << 17); /* Bit 17: Tx Warning Interrupt Flag */
404 constexpr unsigned long ESR1_SYNCH = (1U << 18); /* Bit 18: CAN Synchronization Status */
405 /* Bits 19-31: Reserved */
406 /* Interrupt Masks 2 Register */
407 
408 constexpr unsigned long CAN_IMASK2_0 = (1U << 0); /* Bit 0: Buffer MB0 Mask */
409 constexpr unsigned long CAN_IMASK2_1 = (1U << 1); /* Bit 1: Buffer MB1 Mask */
410 constexpr unsigned long CAN_IMASK2_2 = (1U << 2); /* Bit 2: Buffer MB2 Mask */
411 constexpr unsigned long CAN_IMASK2_3 = (1U << 3); /* Bit 3: Buffer MB3 Mask */
412 constexpr unsigned long CAN_IMASK2_4 = (1U << 4); /* Bit 4: Buffer MB4 Mask */
413 constexpr unsigned long CAN_IMASK2_5 = (1U << 5); /* Bit 5: Buffer MB5 Mask */
414 constexpr unsigned long CAN_IMASK2_6 = (1U << 6); /* Bit 6: Buffer MB6 Mask */
415 constexpr unsigned long CAN_IMASK2_7 = (1U << 7); /* Bit 7: Buffer MB7 Mask */
416 constexpr unsigned long CAN_IMASK2_8 = (1U << 8); /* Bit 8: Buffer MB8 Mask */
417 constexpr unsigned long CAN_IMASK2_9 = (1U << 9); /* Bit 9: Buffer MB9 Mask */
418 constexpr unsigned long CAN_IMASK2_10 = (1U << 10); /* Bit 10: Buffer MB10 Mask */
419 constexpr unsigned long CAN_IMASK2_11 = (1U << 11); /* Bit 11: Buffer MB11 Mask */
420 constexpr unsigned long CAN_IMASK2_12 = (1U << 12); /* Bit 12: Buffer MB12 Mask */
421 constexpr unsigned long CAN_IMASK2_13 = (1U << 13); /* Bit 13: Buffer MB13 Mask */
422 constexpr unsigned long CAN_IMASK2_14 = (1U << 14); /* Bit 14: Buffer MB14 Mask */
423 constexpr unsigned long CAN_IMASK2_15 = (1U << 15); /* Bit 15: Buffer MB15 Mask */
424 constexpr unsigned long CAN_IMASK2_16 = (1U << 16); /* Bit 16: Buffer MB16 Mask */
425 constexpr unsigned long CAN_IMASK2_17 = (1U << 17); /* Bit 17: Buffer MB17 Mask */
426 constexpr unsigned long CAN_IMASK2_18 = (1U << 18); /* Bit 18: Buffer MB18 Mask */
427 constexpr unsigned long CAN_IMASK2_19 = (1U << 19); /* Bit 19: Buffer MB19 Mask */
428 constexpr unsigned long CAN_IMASK2_20 = (1U << 20); /* Bit 20: Buffer MB20 Mask */
429 constexpr unsigned long CAN_IMASK2_21 = (1U << 21); /* Bit 21: Buffer MB21 Mask */
430 constexpr unsigned long CAN_IMASK2_22 = (1U << 22); /* Bit 22: Buffer MB22 Mask */
431 constexpr unsigned long CAN_IMASK2_23 = (1U << 23); /* Bit 23: Buffer MB23 Mask */
432 constexpr unsigned long CAN_IMASK2_24 = (1U << 24); /* Bit 24: Buffer MB24 Mask */
433 constexpr unsigned long CAN_IMASK2_25 = (1U << 25); /* Bit 25: Buffer MB25 Mask */
434 constexpr unsigned long CAN_IMASK2_26 = (1U << 26); /* Bit 26: Buffer MB26 Mask */
435 constexpr unsigned long CAN_IMASK2_27 = (1U << 27); /* Bit 27: Buffer MB27 Mask */
436 constexpr unsigned long CAN_IMASK2_28 = (1U << 28); /* Bit 28: Buffer MB28 Mask */
437 constexpr unsigned long CAN_IMASK2_29 = (1U << 29); /* Bit 29: Buffer MB29 Mask */
438 constexpr unsigned long CAN_IMASK2_30 = (1U << 30); /* Bit 30: Buffer MB30 Mask */
439 constexpr unsigned long CAN_IMASK2_31 = (1U << 31); /* Bit 31: Buffer MB31 Mask */
440 
441 /* Interrupt Masks 1 Register */
442 
443 constexpr unsigned long CAN_IMASK1_0 = (1U << 0); /* Bit 0: Buffer MB0 Mask */
444 constexpr unsigned long CAN_IMASK1_1 = (1U << 1); /* Bit 1: Buffer MB1 Mask */
445 constexpr unsigned long CAN_IMASK1_2 = (1U << 2); /* Bit 2: Buffer MB2 Mask */
446 constexpr unsigned long CAN_IMASK1_3 = (1U << 3); /* Bit 3: Buffer MB3 Mask */
447 constexpr unsigned long CAN_IMASK1_4 = (1U << 4); /* Bit 4: Buffer MB4 Mask */
448 constexpr unsigned long CAN_IMASK1_5 = (1U << 5); /* Bit 5: Buffer MB5 Mask */
449 constexpr unsigned long CAN_IMASK1_6 = (1U << 6); /* Bit 6: Buffer MB6 Mask */
450 constexpr unsigned long CAN_IMASK1_7 = (1U << 7); /* Bit 7: Buffer MB7 Mask */
451 constexpr unsigned long CAN_IMASK1_8 = (1U << 8); /* Bit 8: Buffer MB8 Mask */
452 constexpr unsigned long CAN_IMASK1_9 = (1U << 9); /* Bit 9: Buffer MB9 Mask */
453 constexpr unsigned long CAN_IMASK1_10 = (1U << 10); /* Bit 10: Buffer MB10 Mask */
454 constexpr unsigned long CAN_IMASK1_11 = (1U << 11); /* Bit 11: Buffer MB11 Mask */
455 constexpr unsigned long CAN_IMASK1_12 = (1U << 12); /* Bit 12: Buffer MB12 Mask */
456 constexpr unsigned long CAN_IMASK1_13 = (1U << 13); /* Bit 13: Buffer MB13 Mask */
457 constexpr unsigned long CAN_IMASK1_14 = (1U << 14); /* Bit 14: Buffer MB14 Mask */
458 constexpr unsigned long CAN_IMASK1_15 = (1U << 15); /* Bit 15: Buffer MB15 Mask */
459 constexpr unsigned long CAN_IMASK1_16 = (1U << 16); /* Bit 16: Buffer MB16 Mask */
460 constexpr unsigned long CAN_IMASK1_17 = (1U << 17); /* Bit 17: Buffer MB17 Mask */
461 constexpr unsigned long CAN_IMASK1_18 = (1U << 18); /* Bit 18: Buffer MB18 Mask */
462 constexpr unsigned long CAN_IMASK1_19 = (1U << 19); /* Bit 19: Buffer MB19 Mask */
463 constexpr unsigned long CAN_IMASK1_20 = (1U << 20); /* Bit 20: Buffer MB20 Mask */
464 constexpr unsigned long CAN_IMASK1_21 = (1U << 21); /* Bit 21: Buffer MB21 Mask */
465 constexpr unsigned long CAN_IMASK1_22 = (1U << 22); /* Bit 22: Buffer MB22 Mask */
466 constexpr unsigned long CAN_IMASK1_23 = (1U << 23); /* Bit 23: Buffer MB23 Mask */
467 constexpr unsigned long CAN_IMASK1_24 = (1U << 24); /* Bit 24: Buffer MB24 Mask */
468 constexpr unsigned long CAN_IMASK1_25 = (1U << 25); /* Bit 25: Buffer MB25 Mask */
469 constexpr unsigned long CAN_IMASK1_26 = (1U << 26); /* Bit 26: Buffer MB26 Mask */
470 constexpr unsigned long CAN_IMASK1_27 = (1U << 27); /* Bit 27: Buffer MB27 Mask */
471 constexpr unsigned long CAN_IMASK1_28 = (1U << 28); /* Bit 28: Buffer MB28 Mask */
472 constexpr unsigned long CAN_IMASK1_29 = (1U << 29); /* Bit 29: Buffer MB29 Mask */
473 constexpr unsigned long CAN_IMASK1_30 = (1U << 30); /* Bit 30: Buffer MB30 Mask */
474 constexpr unsigned long CAN_IMASK1_31 = (1U << 31); /* Bit 31: Buffer MB31 Mask */
475 
476 /* Interrupt Flags 2 Register */
477 
478 constexpr unsigned long CAN_IFLAG2_0 = (1U << 0); /* Bit 0: Buffer MB0 Interrupt */
479 constexpr unsigned long CAN_IFLAG2_1 = (1U << 1); /* Bit 1: Buffer MB1 Interrupt */
480 constexpr unsigned long CAN_IFLAG2_2 = (1U << 2); /* Bit 2: Buffer MB2 Interrupt */
481 constexpr unsigned long CAN_IFLAG2_3 = (1U << 3); /* Bit 3: Buffer MB3 Interrupt */
482 constexpr unsigned long CAN_IFLAG2_4 = (1U << 4); /* Bit 4: Buffer MB4 Interrupt */
483 constexpr unsigned long CAN_IFLAG2_5 = (1U << 5); /* Bit 5: Buffer MB5 Interrupt */
484 constexpr unsigned long CAN_IFLAG2_6 = (1U << 6); /* Bit 6: Buffer MB6 Interrupt */
485 constexpr unsigned long CAN_IFLAG2_7 = (1U << 7); /* Bit 7: Buffer MB7 Interrupt */
486 constexpr unsigned long CAN_IFLAG2_8 = (1U << 8); /* Bit 8: Buffer MB8 Interrupt */
487 constexpr unsigned long CAN_IFLAG2_9 = (1U << 9); /* Bit 9: Buffer MB9 Interrupt */
488 constexpr unsigned long CAN_IFLAG2_10 = (1U << 10); /* Bit 10: Buffer MB10 Interrupt */
489 constexpr unsigned long CAN_IFLAG2_11 = (1U << 11); /* Bit 11: Buffer MB11 Interrupt */
490 constexpr unsigned long CAN_IFLAG2_12 = (1U << 12); /* Bit 12: Buffer MB12 Interrupt */
491 constexpr unsigned long CAN_IFLAG2_13 = (1U << 13); /* Bit 13: Buffer MB13 Interrupt */
492 constexpr unsigned long CAN_IFLAG2_14 = (1U << 14); /* Bit 14: Buffer MB14 Interrupt */
493 constexpr unsigned long CAN_IFLAG2_15 = (1U << 15); /* Bit 15: Buffer MB15 Interrupt */
494 constexpr unsigned long CAN_IFLAG2_16 = (1U << 16); /* Bit 16: Buffer MB16 Interrupt */
495 constexpr unsigned long CAN_IFLAG2_17 = (1U << 17); /* Bit 17: Buffer MB17 Interrupt */
496 constexpr unsigned long CAN_IFLAG2_18 = (1U << 18); /* Bit 18: Buffer MB18 Interrupt */
497 constexpr unsigned long CAN_IFLAG2_19 = (1U << 19); /* Bit 19: Buffer MB19 Interrupt */
498 constexpr unsigned long CAN_IFLAG2_20 = (1U << 20); /* Bit 20: Buffer MB20 Interrupt */
499 constexpr unsigned long CAN_IFLAG2_21 = (1U << 21); /* Bit 21: Buffer MB21 Interrupt */
500 constexpr unsigned long CAN_IFLAG2_22 = (1U << 22); /* Bit 22: Buffer MB22 Interrupt */
501 constexpr unsigned long CAN_IFLAG2_23 = (1U << 23); /* Bit 23: Buffer MB23 Interrupt */
502 constexpr unsigned long CAN_IFLAG2_24 = (1U << 24); /* Bit 24: Buffer MB24 Interrupt */
503 constexpr unsigned long CAN_IFLAG2_25 = (1U << 25); /* Bit 25: Buffer MB25 Interrupt */
504 constexpr unsigned long CAN_IFLAG2_26 = (1U << 26); /* Bit 26: Buffer MB26 Interrupt */
505 constexpr unsigned long CAN_IFLAG2_27 = (1U << 27); /* Bit 27: Buffer MB27 Interrupt */
506 constexpr unsigned long CAN_IFLAG2_28 = (1U << 28); /* Bit 28: Buffer MB28 Interrupt */
507 constexpr unsigned long CAN_IFLAG2_29 = (1U << 29); /* Bit 29: Buffer MB29 Interrupt */
508 constexpr unsigned long CAN_IFLAG2_30 = (1U << 30); /* Bit 30: Buffer MB30 Interrupt */
509 constexpr unsigned long CAN_IFLAG2_31 = (1U << 31); /* Bit 31: Buffer MB31 Interrupt */
510 
511 /* Interrupt Flags 1 Register */
512 
513 constexpr unsigned long CAN_IFLAG1_0 = (1U << 0); /* Bit 0: Buffer MB0 Interrupt */
514 constexpr unsigned long CAN_IFLAG1_1 = (1U << 1); /* Bit 1: Buffer MB1 Interrupt */
515 constexpr unsigned long CAN_IFLAG1_2 = (1U << 2); /* Bit 2: Buffer MB2 Interrupt */
516 constexpr unsigned long CAN_IFLAG1_3 = (1U << 3); /* Bit 3: Buffer MB3 Interrupt */
517 constexpr unsigned long CAN_IFLAG1_4 = (1U << 4); /* Bit 4: Buffer MB4 Interrupt */
518 constexpr unsigned long CAN_IFLAG1_5 = (1U << 5); /* Bit 5: Buffer MB5 Interrupt */
519 constexpr unsigned long CAN_FIFO_NE = CAN_IFLAG1_5; /* Bit 5: Fifo almost Not empty Interrupt */
520 constexpr unsigned long CAN_IFLAG1_6 = (1U << 6); /* Bit 6: Buffer MB6 Interrupt */
521 constexpr unsigned long CAN_FIFO_WARN = CAN_IFLAG1_6; /* Bit 6: Fifo almost full Interrupt */
522 constexpr unsigned long CAN_IFLAG1_7 = (1U << 7); /* Bit 7: Buffer MB7 Interrupt */
523 constexpr unsigned long CAN_FIFO_OV = CAN_IFLAG1_7; /* Bit 7: Fifo Overflowed Interrupt */
524 constexpr unsigned long CAN_IFLAG1_8 = (1U << 8); /* Bit 8: Buffer MB8 Interrupt */
525 constexpr unsigned long CAN_IFLAG1_9 = (1U << 9); /* Bit 9: Buffer MB9 Interrupt */
526 constexpr unsigned long CAN_IFLAG1_10 = (1U << 10); /* Bit 10: Buffer MB10 Interrupt */
527 constexpr unsigned long CAN_IFLAG1_11 = (1U << 11); /* Bit 11: Buffer MB11 Interrupt */
528 constexpr unsigned long CAN_IFLAG1_12 = (1U << 12); /* Bit 12: Buffer MB12 Interrupt */
529 constexpr unsigned long CAN_IFLAG1_13 = (1U << 13); /* Bit 13: Buffer MB13 Interrupt */
530 constexpr unsigned long CAN_IFLAG1_14 = (1U << 14); /* Bit 14: Buffer MB14 Interrupt */
531 constexpr unsigned long CAN_IFLAG1_15 = (1U << 15); /* Bit 15: Buffer MB15 Interrupt */
532 constexpr unsigned long CAN_IFLAG1_16 = (1U << 16); /* Bit 16: Buffer MB16 Interrupt */
533 constexpr unsigned long CAN_IFLAG1_17 = (1U << 17); /* Bit 17: Buffer MB17 Interrupt */
534 constexpr unsigned long CAN_IFLAG1_18 = (1U << 18); /* Bit 18: Buffer MB18 Interrupt */
535 constexpr unsigned long CAN_IFLAG1_19 = (1U << 19); /* Bit 19: Buffer MB19 Interrupt */
536 constexpr unsigned long CAN_IFLAG1_20 = (1U << 20); /* Bit 20: Buffer MB20 Interrupt */
537 constexpr unsigned long CAN_IFLAG1_21 = (1U << 21); /* Bit 21: Buffer MB21 Interrupt */
538 constexpr unsigned long CAN_IFLAG1_22 = (1U << 22); /* Bit 22: Buffer MB22 Interrupt */
539 constexpr unsigned long CAN_IFLAG1_23 = (1U << 23); /* Bit 23: Buffer MB23 Interrupt */
540 constexpr unsigned long CAN_IFLAG1_24 = (1U << 24); /* Bit 24: Buffer MB24 Interrupt */
541 constexpr unsigned long CAN_IFLAG1_25 = (1U << 25); /* Bit 25: Buffer MB25 Interrupt */
542 constexpr unsigned long CAN_IFLAG1_26 = (1U << 26); /* Bit 26: Buffer MB26 Interrupt */
543 constexpr unsigned long CAN_IFLAG1_27 = (1U << 27); /* Bit 27: Buffer MB27 Interrupt */
544 constexpr unsigned long CAN_IFLAG1_28 = (1U << 28); /* Bit 28: Buffer MB28 Interrupt */
545 constexpr unsigned long CAN_IFLAG1_29 = (1U << 29); /* Bit 29: Buffer MB29 Interrupt */
546 constexpr unsigned long CAN_IFLAG1_30 = (1U << 30); /* Bit 30: Buffer MB30 Interrupt */
547 constexpr unsigned long CAN_IFLAG1_31 = (1U << 31); /* Bit 31: Buffer MB31 Interrupt */
548 
549 /* Control 2 Register */
550 /* Bits 0-15: Reserved */
551 constexpr unsigned long CTRL2_EACEN = (1U << 16); /* Bit 16: Entire Frame Arbitration Field Comparison
552  Enable (Rx) */
553 constexpr unsigned long CTRL2_RRS = (1U << 17); /* Bit 17: Remote Request Storing */
554 constexpr unsigned long CTRL2_MRP = (1U << 18); /* Bit 18: Mailboxes Reception Priority */
555 constexpr unsigned long CTRL2_TASD_SHIFT = (19); /* Bits 19-23: Tx Arbitration Start Delay */
556 constexpr unsigned long CTRL2_TASD_MASK = (31U << CTRL2_TASD_SHIFT);
557 constexpr unsigned long CTRL2_RFFN_SHIFT = (24); /* Bits 24-27: Number of Rx FIFO Filters */
558 constexpr unsigned long CTRL2_RFFN_MASK(15U << CTRL2_RFFN_SHIFT);
559 constexpr unsigned long CTRL2_RFFN_8MB(0U << CTRL2_RFFN_SHIFT);
560 constexpr unsigned long CTRL2_RFFN_16MB(1U << CTRL2_RFFN_SHIFT);
561 constexpr unsigned long CTRL2_RFFN_24MB(2U << CTRL2_RFFN_SHIFT);
562 constexpr unsigned long CTRL2_RFFN_32MB(3U << CTRL2_RFFN_SHIFT);
563 constexpr unsigned long CTRL2_RFFN_40MB(4U << CTRL2_RFFN_SHIFT);
564 constexpr unsigned long CTRL2_RFFN_48MB(5U << CTRL2_RFFN_SHIFT);
565 constexpr unsigned long CTRL2_RFFN_56MB(6U << CTRL2_RFFN_SHIFT);
566 constexpr unsigned long CTRL2_RFFN_64MB(7U << CTRL2_RFFN_SHIFT);
567 constexpr unsigned long CTRL2_RFFN_72MB(8U << CTRL2_RFFN_SHIFT);
568 constexpr unsigned long CTRL2_RFFN_80MB(9U << CTRL2_RFFN_SHIFT);
569 constexpr unsigned long CTRL2_RFFN_88MB(10U << CTRL2_RFFN_SHIFT);
570 constexpr unsigned long CTRL2_RFFN_96MB(11U << CTRL2_RFFN_SHIFT);
571 constexpr unsigned long CTRL2_RFFN_104MB(12U << CTRL2_RFFN_SHIFT);
572 constexpr unsigned long CTRL2_RFFN_112MB(13U << CTRL2_RFFN_SHIFT);
573 constexpr unsigned long CTRL2_RFFN_120MB(14U << CTRL2_RFFN_SHIFT);
574 constexpr unsigned long CTRL2_RFFN_128MB(15U << CTRL2_RFFN_SHIFT);
575 constexpr unsigned long CTRL2_WRMFRZ = (1U << 28U); /* Bit 28: Write-Access to Memory in Freeze mode */
576 /* Bits 29-31: Reserved */
577 
578 /* Error and Status 2 Register */
579 /* Bits 0-12: Reserved */
580 constexpr unsigned long ESR2_IMB = (1U << 13); /* Bit 13: Inactive Mailbox */
581 constexpr unsigned long ESR2_VPS = (1U << 14); /* Bit 14: Valid Priority Status */
582 /* Bit 15: Reserved */
583 constexpr unsigned long ESR2_LPTM_SHIFT = (16); /* Bits 16-22: Lowest Priority Tx Mailbox */
584 constexpr unsigned long ESR2_LPTM_MASK = (0x7fU << ESR2_LPTM_SHIFT);
585 /* Bits 23-31: Reserved */
586 /* CRC Register */
587 
588 constexpr unsigned long CRCR_TXCRC_SHIFT = (0U); /* Bits 0-14: CRC Transmitted */
589 constexpr unsigned long CRCR_TXCRC_MASK = (0x7fffU << CRCR_TXCRC_SHIFT); /* Rx FIFO Global Mask Register (32 Rx
590  FIFO Global Mask Bits) */
591 /* Bits 23-31: Reserved */
592 constexpr unsigned long CRCR_MBCRC_SHIFT = (16); /* Bits 16-22: CRC Mailbox */
593 constexpr unsigned long CRCR_MBCRC_MASK = (0x7fU << CRCR_MBCRC_SHIFT);
594 /* Bit 15: Reserved */
595 
596 /* Rx FIFO Information Register */
597 /* Bits 9-31: Reserved */
598 constexpr unsigned long RXFIR_IDHIT_SHIFT = (0); /* Bits 0-8: Identifier Acceptance Filter Hit Indicator
599  */
600 constexpr unsigned long RXFIR_IDHIT_MASK = (0x1ffU << RXFIR_IDHIT_SHIFT);
601 
602 /* Rn Individual Mask Registers */
603 
604 constexpr unsigned long RXIMR0 = (1U << 0); /* Bit 0: Individual Mask Bits */
605 constexpr unsigned long RXIMR1 = (1U << 1); /* Bit 1: Individual Mask Bits */
606 constexpr unsigned long RXIMR2 = (1U << 2); /* Bit 2: Individual Mask Bits */
607 constexpr unsigned long RXIMR3 = (1U << 3); /* Bit 3: Individual Mask Bits */
608 constexpr unsigned long RXIMR4 = (1U << 4); /* Bit 4: Individual Mask Bits */
609 constexpr unsigned long RXIMR5 = (1U << 5); /* Bit 5: Individual Mask Bits */
610 constexpr unsigned long RXIMR6 = (1U << 6); /* Bit 6: Individual Mask Bits */
611 constexpr unsigned long RXIMR7 = (1U << 7); /* Bit 7: Individual Mask Bits */
612 constexpr unsigned long RXIMR8 = (1U << 8); /* Bit 8: Individual Mask Bits */
613 constexpr unsigned long RXIMR9 = (1U << 9); /* Bit 9: Individual Mask Bits */
614 constexpr unsigned long RXIMR10 = (1U << 10); /* Bit 10: Individual Mask Bits */
615 constexpr unsigned long RXIMR11 = (1U << 11); /* Bit 11: Individual Mask Bits */
616 constexpr unsigned long RXIMR12 = (1U << 12); /* Bit 12: Individual Mask Bits */
617 constexpr unsigned long RXIMR13 = (1U << 13); /* Bit 13: Individual Mask Bits */
618 constexpr unsigned long RXIMR14 = (1U << 14); /* Bit 14: Individual Mask Bits */
619 constexpr unsigned long RXIMR15 = (1U << 15); /* Bit 15: Individual Mask Bits */
620 constexpr unsigned long RXIMR16 = (1U << 16); /* Bit 16: Individual Mask Bits */
621 constexpr unsigned long RXIMR17 = (1U << 17); /* Bit 17: Individual Mask Bits */
622 constexpr unsigned long RXIMR18 = (1U << 18); /* Bit 18: Individual Mask Bits */
623 constexpr unsigned long RXIMR19 = (1U << 19); /* Bit 19: Individual Mask Bits */
624 constexpr unsigned long RXIMR20 = (1U << 20); /* Bit 20: Individual Mask Bits */
625 constexpr unsigned long RXIMR21 = (1U << 21); /* Bit 21: Individual Mask Bits */
626 constexpr unsigned long RXIMR22 = (1U << 22); /* Bit 22: Individual Mask Bits */
627 constexpr unsigned long RXIMR23 = (1U << 23); /* Bit 23: Individual Mask Bits */
628 constexpr unsigned long RXIMR24 = (1U << 24); /* Bit 24: Individual Mask Bits */
629 constexpr unsigned long RXIMR25 = (1U << 25); /* Bit 25: Individual Mask Bits */
630 constexpr unsigned long RXIMR26 = (1U << 26); /* Bit 26: Individual Mask Bits */
631 constexpr unsigned long RXIMR27 = (1U << 27); /* Bit 27: Individual Mask Bits */
632 constexpr unsigned long RXIMR28 = (1U << 28); /* Bit 28: Individual Mask Bits */
633 constexpr unsigned long RXIMR29 = (1U << 29); /* Bit 29: Individual Mask Bits */
634 constexpr unsigned long RXIMR30 = (1U << 30); /* Bit 30: Individual Mask Bits */
635 constexpr unsigned long RXIMR31 = (1U << 31); /* Bit 31: Individual Mask Bits */
636 }
637 }
638 
639 #if UAVCAN_CPP_VERSION < UAVCAN_CPP11
640 # undef constexpr
641 #endif
constexpr unsigned long CAN_IMASK2_15
Definition: flexcan.hpp:423
constexpr unsigned long CTRL2_RFFN_56MB(6U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long CAN_IMASK1_28
Definition: flexcan.hpp:471
constexpr unsigned long CAN_IMASK2_24
Definition: flexcan.hpp:432
constexpr unsigned long MCR_IDAM_MASK
Definition: flexcan.hpp:212
constexpr unsigned long CAN_IMASK1_27
Definition: flexcan.hpp:470
constexpr unsigned long ESR1_FRMERR
Definition: flexcan.hpp:397
constexpr unsigned long CTRL2_TASD_MASK
Definition: flexcan.hpp:556
constexpr unsigned long CAN_IFLAG2_13
Definition: flexcan.hpp:491
constexpr unsigned long CAN_IMASK1_10
Definition: flexcan.hpp:453
constexpr unsigned long ESR1_BOFFINT
Definition: flexcan.hpp:385
constexpr unsigned long CAN_IMASK2_25
Definition: flexcan.hpp:433
constexpr unsigned long CTRL1_LPB
Definition: flexcan.hpp:250
constexpr unsigned long RXIMR31
Definition: flexcan.hpp:635
constexpr unsigned long MCR_FRZACK
Definition: flexcan.hpp:229
constexpr unsigned long ESR1_RX
Definition: flexcan.hpp:386
constexpr unsigned long RXMGMASK30
Definition: flexcan.hpp:300
constexpr unsigned long RXM14MASK31
Definition: flexcan.hpp:336
constexpr unsigned long RXMGMASK21
Definition: flexcan.hpp:291
constexpr unsigned long CAN_IFLAG1_24
Definition: flexcan.hpp:540
constexpr unsigned long CAN_IFLAG2_2
Definition: flexcan.hpp:480
constexpr unsigned long CAN_IFLAG2_15
Definition: flexcan.hpp:493
constexpr unsigned long CAN_IMASK1_2
Definition: flexcan.hpp:445
constexpr unsigned long CAN_IFLAG1_5
Definition: flexcan.hpp:518
constexpr unsigned long RXM15MASK13
Definition: flexcan.hpp:353
constexpr unsigned long ESR1_RWRNINT
Definition: flexcan.hpp:402
constexpr unsigned long CAN_IMASK2_4
Definition: flexcan.hpp:412
constexpr unsigned long CAN_IMASK1_0
Definition: flexcan.hpp:443
constexpr unsigned long CAN_IMASK1_6
Definition: flexcan.hpp:449
constexpr unsigned long MCR_FRZ
Definition: flexcan.hpp:235
constexpr unsigned long RXM14MASK20
Definition: flexcan.hpp:325
constexpr unsigned long RXM15MASK28
Definition: flexcan.hpp:368
constexpr unsigned long CTRL2_MRP
Definition: flexcan.hpp:554
constexpr unsigned long CAN_IFLAG1_14
Definition: flexcan.hpp:530
constexpr unsigned long RXMGMASK2
Definition: flexcan.hpp:272
constexpr unsigned long CAN_IFLAG2_22
Definition: flexcan.hpp:500
constexpr unsigned long CAN_IMASK2_17
Definition: flexcan.hpp:425
constexpr unsigned long CTRL2_RFFN_96MB(11U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long CTRL2_RFFN_104MB(12U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long CAN_IMASK1_31
Definition: flexcan.hpp:474
constexpr unsigned long RXM15MASK5
Definition: flexcan.hpp:345
constexpr unsigned long CTRL1_ROPSEG_MASK
Definition: flexcan.hpp:241
constexpr unsigned long CAN_IMASK2_2
Definition: flexcan.hpp:410
constexpr unsigned long CTRL1_ROPSEG_SHIFT
Definition: flexcan.hpp:240
constexpr unsigned long ESR1_WAKINT
Definition: flexcan.hpp:383
constexpr unsigned long RXM15MASK25
Definition: flexcan.hpp:365
constexpr unsigned long ECR_RXERRCNT_SHIFT
Definition: flexcan.hpp:377
constexpr unsigned long CAN_IMASK2_5
Definition: flexcan.hpp:413
constexpr unsigned long CTRL1_TSYN
Definition: flexcan.hpp:244
constexpr unsigned long CAN_IMASK2_19
Definition: flexcan.hpp:427
constexpr unsigned long ESR1_FLTCONF_ACTV
Definition: flexcan.hpp:389
volatile uint32_t resstd
Definition: flexcan.hpp:64
constexpr unsigned long RXFIR_IDHIT_SHIFT
Definition: flexcan.hpp:598
constexpr unsigned long ESR1_RXWRN
Definition: flexcan.hpp:394
constexpr unsigned long CTRL2_RFFN_48MB(5U<< CTRL2_RFFN_SHIFT)
volatile uint32_t resex
Definition: flexcan.hpp:59
constexpr unsigned long RXM15MASK11
Definition: flexcan.hpp:351
constexpr unsigned long RXM14MASK30
Definition: flexcan.hpp:335
constexpr unsigned long RXM15MASK0
Definition: flexcan.hpp:340
constexpr unsigned long RXIMR15
Definition: flexcan.hpp:619
constexpr unsigned long CAN_IMASK1_11
Definition: flexcan.hpp:454
constexpr unsigned long MCR_IDAM_FMTD(3U<< MCR_IDAM_SHIFT)
constexpr unsigned long MCR_SRXDIS
Definition: flexcan.hpp:222
constexpr unsigned long CAN_IFLAG1_25
Definition: flexcan.hpp:541
constexpr unsigned long CAN_IFLAG1_2
Definition: flexcan.hpp:515
constexpr unsigned long MCR_IDAM_FMTA(0U<< MCR_IDAM_SHIFT)
constexpr unsigned long CAN_IFLAG2_23
Definition: flexcan.hpp:501
volatile uint32_t RX15MASK
Definition: flexcan.hpp:142
constexpr unsigned long RXMGMASK17
Definition: flexcan.hpp:287
constexpr unsigned long RXM14MASK26
Definition: flexcan.hpp:331
constexpr unsigned long RXM15MASK9
Definition: flexcan.hpp:349
constexpr unsigned long CAN_IFLAG1_17
Definition: flexcan.hpp:533
constexpr unsigned long CAN_IMASK1_7
Definition: flexcan.hpp:450
constexpr unsigned long MCR_MAXMB_MASK
Definition: flexcan.hpp:209
constexpr unsigned long CTRL2_RFFN_72MB(8U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long CAN_IFLAG1_20
Definition: flexcan.hpp:536
constexpr unsigned long RXM14MASK19
Definition: flexcan.hpp:324
constexpr unsigned long CAN_IMASK2_6
Definition: flexcan.hpp:414
constexpr unsigned long RXIMR23
Definition: flexcan.hpp:627
constexpr unsigned long RXMGMASK15
Definition: flexcan.hpp:285
constexpr unsigned long RXM15MASK17
Definition: flexcan.hpp:357
constexpr unsigned long CTRL2_RFFN_SHIFT
Definition: flexcan.hpp:557
constexpr unsigned long CAN_IMASK2_3
Definition: flexcan.hpp:411
constexpr unsigned long CAN_IMASK1_8
Definition: flexcan.hpp:451
constexpr unsigned long RXM15MASK10
Definition: flexcan.hpp:350
constexpr unsigned long CAN_IMASK2_28
Definition: flexcan.hpp:436
constexpr unsigned long CAN_IFLAG1_30
Definition: flexcan.hpp:546
constexpr unsigned long MCR_MDIS
Definition: flexcan.hpp:236
constexpr unsigned long RXIMR6
Definition: flexcan.hpp:610
constexpr unsigned long RXMGMASK20
Definition: flexcan.hpp:290
constexpr unsigned long RXM14MASK23
Definition: flexcan.hpp:328
constexpr unsigned long CTRL2_RFFN_64MB(7U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long CAN_IFLAG2_18
Definition: flexcan.hpp:496
constexpr unsigned long CAN_FIFO_NE
Definition: flexcan.hpp:519
constexpr unsigned long RXM14MASK12
Definition: flexcan.hpp:317
constexpr unsigned long RXM15MASK22
Definition: flexcan.hpp:362
constexpr unsigned long ESR1_TWRNINT
Definition: flexcan.hpp:403
constexpr unsigned long RXMGMASK22
Definition: flexcan.hpp:292
constexpr unsigned long RXFIR_IDHIT_MASK
Definition: flexcan.hpp:600
constexpr unsigned long RXIMR19
Definition: flexcan.hpp:623
constexpr unsigned long CAN_IMASK2_16
Definition: flexcan.hpp:424
constexpr unsigned long CAN_IMASK2_1
Definition: flexcan.hpp:409
constexpr unsigned long CAN_IMASK2_22
Definition: flexcan.hpp:430
constexpr unsigned long CTRL2_TASD_SHIFT
Definition: flexcan.hpp:555
constexpr unsigned long MCR_LPRIOEN
Definition: flexcan.hpp:219
constexpr unsigned long RXMGMASK8
Definition: flexcan.hpp:278
constexpr unsigned long RXMGMASK16
Definition: flexcan.hpp:286
constexpr unsigned long CAN_IMASK1_19
Definition: flexcan.hpp:462
constexpr unsigned long CTRL1_RJW_SHIFT
Definition: flexcan.hpp:258
constexpr unsigned long CAN_IMASK2_27
Definition: flexcan.hpp:435
constexpr unsigned long CAN_IFLAG2_0
Definition: flexcan.hpp:478
constexpr unsigned long RXM15MASK15
Definition: flexcan.hpp:355
constexpr unsigned long CAN_IMASK1_23
Definition: flexcan.hpp:466
constexpr unsigned long CAN_IMASK1_20
Definition: flexcan.hpp:463
constexpr unsigned long RXM14MASK16
Definition: flexcan.hpp:321
constexpr unsigned long CAN_IFLAG2_4
Definition: flexcan.hpp:482
constexpr unsigned long ESR1_FLTCONF_OFF
Definition: flexcan.hpp:391
constexpr unsigned long RXM15MASK19
Definition: flexcan.hpp:359
constexpr unsigned long RXM14MASK8
Definition: flexcan.hpp:313
constexpr unsigned long RXMGMASK9
Definition: flexcan.hpp:279
constexpr unsigned long RXMGMASK5
Definition: flexcan.hpp:275
constexpr unsigned long CTRL1_TWRNMSK
Definition: flexcan.hpp:249
constexpr unsigned long CAN_IMASK1_26
Definition: flexcan.hpp:469
constexpr unsigned long CAN_IFLAG2_30
Definition: flexcan.hpp:508
constexpr unsigned long RXM15MASK20
Definition: flexcan.hpp:360
constexpr unsigned long CTRL1_PSEG1_SHIFT
Definition: flexcan.hpp:256
constexpr unsigned long ESR1_SYNCH
Definition: flexcan.hpp:404
constexpr unsigned long CAN_IMASK2_21
Definition: flexcan.hpp:429
constexpr unsigned long CTRL1_PSEG2_SHIFT
Definition: flexcan.hpp:254
constexpr unsigned long RXM14MASK28
Definition: flexcan.hpp:333
constexpr unsigned long RXM14MASK24
Definition: flexcan.hpp:329
constexpr unsigned long CAN_IMASK1_29
Definition: flexcan.hpp:472
constexpr unsigned long RXIMR8
Definition: flexcan.hpp:612
constexpr unsigned long CRCR_MBCRC_SHIFT
Definition: flexcan.hpp:592
constexpr unsigned long RXM14MASK9
Definition: flexcan.hpp:314
volatile uint32_t RXFGMASK
Definition: flexcan.hpp:154
constexpr unsigned long RXM15MASK12
Definition: flexcan.hpp:352
constexpr unsigned long RXM15MASK4
Definition: flexcan.hpp:344
constexpr unsigned long ESR1_TX
Definition: flexcan.hpp:392
constexpr unsigned long RXMGMASK1
Definition: flexcan.hpp:271
constexpr unsigned long ESR1_TXWRN
Definition: flexcan.hpp:395
constexpr unsigned long RXIMR10
Definition: flexcan.hpp:614
constexpr unsigned long RXIMR2
Definition: flexcan.hpp:606
constexpr unsigned long CAN_IFLAG2_27
Definition: flexcan.hpp:505
constexpr unsigned long RXIMR28
Definition: flexcan.hpp:632
constexpr unsigned long RXIMR0
Definition: flexcan.hpp:604
constexpr unsigned long RXIMR20
Definition: flexcan.hpp:624
constexpr unsigned long RXMGMASK6
Definition: flexcan.hpp:276
constexpr unsigned long CAN_IMASK1_12
Definition: flexcan.hpp:455
constexpr unsigned long CTRL2_RFFN_88MB(10U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long RXMGMASK11
Definition: flexcan.hpp:281
constexpr unsigned long RXIMR1
Definition: flexcan.hpp:605
constexpr unsigned long RXMGMASK27
Definition: flexcan.hpp:297
constexpr unsigned long MCR_IRMQ
Definition: flexcan.hpp:221
constexpr unsigned long CTRL2_RFFN_120MB(14U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long RXMGMASK29
Definition: flexcan.hpp:299
constexpr unsigned long CAN_IMASK2_14
Definition: flexcan.hpp:422
constexpr unsigned long CAN_IFLAG2_7
Definition: flexcan.hpp:485
constexpr unsigned long RXIMR7
Definition: flexcan.hpp:611
constexpr unsigned long ESR1_BIT1ERR
Definition: flexcan.hpp:401
constexpr unsigned long CAN_IFLAG2_6
Definition: flexcan.hpp:484
constexpr unsigned long ECR_TXERRCNT_MASK
Definition: flexcan.hpp:376
constexpr unsigned long RXIMR29
Definition: flexcan.hpp:633
constexpr unsigned long CAN_IFLAG2_12
Definition: flexcan.hpp:490
constexpr unsigned long CTRL2_WRMFRZ
Definition: flexcan.hpp:575
constexpr unsigned long MCR_IDAM_SHIFT
Definition: flexcan.hpp:211
constexpr unsigned long RXMGMASK26
Definition: flexcan.hpp:296
constexpr unsigned long CAN_IMASK2_0
Definition: flexcan.hpp:408
constexpr unsigned long CAN_IFLAG1_1
Definition: flexcan.hpp:514
constexpr unsigned long RXM14MASK11
Definition: flexcan.hpp:316
constexpr unsigned long CAN_IMASK1_4
Definition: flexcan.hpp:447
constexpr unsigned long RXIMR16
Definition: flexcan.hpp:620
constexpr unsigned long RXM14MASK22
Definition: flexcan.hpp:327
constexpr unsigned long CAN_IFLAG2_8
Definition: flexcan.hpp:486
constexpr unsigned long CAN_IFLAG2_24
Definition: flexcan.hpp:502
constexpr unsigned long CAN_IFLAG1_18
Definition: flexcan.hpp:534
constexpr unsigned long CAN_IFLAG1_13
Definition: flexcan.hpp:529
constexpr unsigned long MCR_NOTRDY
Definition: flexcan.hpp:232
constexpr unsigned long CAN_IFLAG2_16
Definition: flexcan.hpp:494
constexpr unsigned long CAN_IFLAG1_6
Definition: flexcan.hpp:520
constexpr unsigned long RXMGMASK18
Definition: flexcan.hpp:288
constexpr unsigned long ESR1_FLTCONF_PASV
Definition: flexcan.hpp:390
constexpr unsigned long CAN_IMASK1_3
Definition: flexcan.hpp:446
constexpr unsigned long CAN_IFLAG1_4
Definition: flexcan.hpp:517
constexpr unsigned long CAN_IFLAG1_21
Definition: flexcan.hpp:537
constexpr unsigned long RXM15MASK29
Definition: flexcan.hpp:369
constexpr unsigned long MCR_SUPV
Definition: flexcan.hpp:228
constexpr unsigned long RXM14MASK6
Definition: flexcan.hpp:311
constexpr unsigned long RXMGMASK13
Definition: flexcan.hpp:283
constexpr unsigned long RXMGMASK3
Definition: flexcan.hpp:273
constexpr unsigned long CAN_IMASK1_9
Definition: flexcan.hpp:452
constexpr unsigned long CAN_IFLAG2_21
Definition: flexcan.hpp:499
constexpr unsigned long CAN_IMASK2_7
Definition: flexcan.hpp:415
constexpr unsigned long CAN_IMASK2_12
Definition: flexcan.hpp:420
constexpr unsigned long CAN_IFLAG1_15
Definition: flexcan.hpp:531
constexpr unsigned long RXM15MASK30
Definition: flexcan.hpp:370
constexpr unsigned long CAN_IMASK2_31
Definition: flexcan.hpp:439
constexpr unsigned long RXM14MASK15
Definition: flexcan.hpp:320
constexpr unsigned long CAN_IFLAG1_19
Definition: flexcan.hpp:535
constexpr unsigned long CAN_IMASK1_24
Definition: flexcan.hpp:467
constexpr unsigned long MCR_IDAM_FMTC(2U<< MCR_IDAM_SHIFT)
constexpr unsigned long CAN_IFLAG2_28
Definition: flexcan.hpp:506
constexpr unsigned long RXM14MASK21
Definition: flexcan.hpp:326
constexpr unsigned long CTRL1_ERRMSK
Definition: flexcan.hpp:252
constexpr unsigned long RXIMR22
Definition: flexcan.hpp:626
constexpr unsigned long CRCR_MBCRC_MASK
Definition: flexcan.hpp:593
constexpr unsigned long RXM15MASK31
Definition: flexcan.hpp:371
constexpr unsigned long CAN_IFLAG1_0
Definition: flexcan.hpp:513
constexpr unsigned long CAN_IMASK1_21
Definition: flexcan.hpp:464
constexpr unsigned long CAN_IMASK1_30
Definition: flexcan.hpp:473
constexpr unsigned long CTRL2_RFFN_24MB(2U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long RXM15MASK7
Definition: flexcan.hpp:347
constexpr unsigned long CAN_IMASK1_22
Definition: flexcan.hpp:465
constexpr unsigned long CAN_IFLAG1_29
Definition: flexcan.hpp:545
constexpr unsigned long RXM15MASK14
Definition: flexcan.hpp:354
constexpr unsigned long CAN_IFLAG2_29
Definition: flexcan.hpp:507
constexpr unsigned long ESR2_IMB
Definition: flexcan.hpp:580
constexpr unsigned long RXM14MASK27
Definition: flexcan.hpp:332
constexpr unsigned long CAN_IMASK1_1
Definition: flexcan.hpp:444
constexpr unsigned long RXIMR9
Definition: flexcan.hpp:613
constexpr unsigned long CAN_IFLAG2_17
Definition: flexcan.hpp:495
constexpr unsigned long CAN_IFLAG1_31
Definition: flexcan.hpp:547
constexpr unsigned long ESR1_CRCERR
Definition: flexcan.hpp:398
constexpr unsigned long CAN_IFLAG2_5
Definition: flexcan.hpp:483
constexpr unsigned long RXM15MASK1
Definition: flexcan.hpp:341
constexpr unsigned long CAN_IFLAG1_23
Definition: flexcan.hpp:539
constexpr unsigned long RXM14MASK3
Definition: flexcan.hpp:308
constexpr unsigned long RXMGMASK23
Definition: flexcan.hpp:293
constexpr unsigned long RXM15MASK23
Definition: flexcan.hpp:363
constexpr unsigned long CAN_IFLAG1_8
Definition: flexcan.hpp:524
constexpr unsigned long RXIMR27
Definition: flexcan.hpp:631
constexpr unsigned long RXM14MASK2
Definition: flexcan.hpp:307
constexpr unsigned long CAN_IFLAG2_31
Definition: flexcan.hpp:509
constexpr unsigned long CAN_IMASK1_18
Definition: flexcan.hpp:461
constexpr unsigned long RXIMR3
Definition: flexcan.hpp:607
constexpr unsigned long CTRL1_RJW_MASK
Definition: flexcan.hpp:259
constexpr unsigned long ESR1_ACKERR
Definition: flexcan.hpp:399
constexpr unsigned long CAN_IMASK2_26
Definition: flexcan.hpp:434
constexpr unsigned long TIMER_MASK
Definition: flexcan.hpp:266
constexpr unsigned long CTRL2_RFFN_32MB(3U<< CTRL2_RFFN_SHIFT)
CanType *const Can[UAVCAN_KINETIS_NUM_IFACES]
CANx register sets.
Definition: flexcan.hpp:198
constexpr unsigned long CAN_IFLAG1_7
Definition: flexcan.hpp:522
constexpr unsigned long CAN_IFLAG2_19
Definition: flexcan.hpp:497
constexpr unsigned long ESR1_STFERR
Definition: flexcan.hpp:396
constexpr unsigned long CRCR_TXCRC_SHIFT
Definition: flexcan.hpp:588
constexpr unsigned long RXIMR5
Definition: flexcan.hpp:609
constexpr unsigned long RXM14MASK0
Definition: flexcan.hpp:305
constexpr unsigned long RXIMR14
Definition: flexcan.hpp:618
constexpr unsigned long CAN_IFLAG1_12
Definition: flexcan.hpp:528
volatile uint32_t RXMGMASK
Definition: flexcan.hpp:140
constexpr unsigned long CAN_IMASK2_9
Definition: flexcan.hpp:417
constexpr unsigned long RXMGMASK10
Definition: flexcan.hpp:280
constexpr unsigned long RXMGMASK19
Definition: flexcan.hpp:289
constexpr unsigned long RXIMR24
Definition: flexcan.hpp:628
constexpr unsigned long CAN_MCR_IDAM_FMTB(1U<< MCR_IDAM_SHIFT)
constexpr unsigned long CTRL1_BOFFMSK
Definition: flexcan.hpp:253
constexpr unsigned long RXMGMASK28
Definition: flexcan.hpp:298
constexpr unsigned long MCR_WAKMSK
Definition: flexcan.hpp:231
volatile uint32_t time_stamp
Definition: flexcan.hpp:32
constexpr unsigned long RXIMR17
Definition: flexcan.hpp:621
constexpr unsigned long CAN_IFLAG1_16
Definition: flexcan.hpp:532
constexpr unsigned long RXM15MASK6
Definition: flexcan.hpp:346
constexpr unsigned long CTRL1_PSEG2_MASK
Definition: flexcan.hpp:255
constexpr unsigned long CTRL2_RFFN_16MB(1U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long RXM15MASK2
Definition: flexcan.hpp:342
constexpr unsigned long CAN_IFLAG1_10
Definition: flexcan.hpp:526
constexpr unsigned long ESR2_LPTM_MASK
Definition: flexcan.hpp:584
constexpr unsigned long RXM14MASK13
Definition: flexcan.hpp:318
constexpr unsigned long CTRL1_BOFFREC
Definition: flexcan.hpp:245
constexpr unsigned long RXMGMASK12
Definition: flexcan.hpp:282
constexpr unsigned long RXM14MASK18
Definition: flexcan.hpp:323
constexpr unsigned long CAN_IMASK2_13
Definition: flexcan.hpp:421
constexpr unsigned long ECR_TXERRCNT_SHIFT
Definition: flexcan.hpp:375
constexpr unsigned long RXM15MASK3
Definition: flexcan.hpp:343
constexpr unsigned long CAN_IFLAG2_20
Definition: flexcan.hpp:498
constexpr unsigned long RXM14MASK17
Definition: flexcan.hpp:322
constexpr unsigned long RXMGMASK24
Definition: flexcan.hpp:294
constexpr unsigned long RXM15MASK16
Definition: flexcan.hpp:356
constexpr unsigned long RXM14MASK5
Definition: flexcan.hpp:310
constexpr unsigned long RXMGMASK14
Definition: flexcan.hpp:284
constexpr unsigned long MCR_AEN
Definition: flexcan.hpp:218
constexpr unsigned long RXMGMASK31
Definition: flexcan.hpp:301
constexpr unsigned long RXM15MASK24
Definition: flexcan.hpp:364
constexpr unsigned long CAN_IFLAG2_9
Definition: flexcan.hpp:487
constexpr unsigned long CTRL1_RWRNMSK
Definition: flexcan.hpp:248
constexpr unsigned long CAN_IFLAG2_3
Definition: flexcan.hpp:481
constexpr unsigned long RXM15MASK27
Definition: flexcan.hpp:367
constexpr unsigned long CTRL1_LOM
Definition: flexcan.hpp:242
constexpr unsigned long CTRL1_PSEG1_MASK
Definition: flexcan.hpp:257
constexpr unsigned long CAN_FIFO_WARN
Definition: flexcan.hpp:521
constexpr unsigned long RXM14MASK14
Definition: flexcan.hpp:319
constexpr unsigned long RXIMR11
Definition: flexcan.hpp:615
constexpr unsigned long RXIMR13
Definition: flexcan.hpp:617
constexpr unsigned long RXM14MASK4
Definition: flexcan.hpp:309
constexpr unsigned long CAN_IFLAG2_26
Definition: flexcan.hpp:504
constexpr unsigned long CAN_IMASK2_23
Definition: flexcan.hpp:431
constexpr unsigned long RXIMR30
Definition: flexcan.hpp:634
constexpr unsigned long ESR1_ERRINT
Definition: flexcan.hpp:384
constexpr unsigned long ESR1_BIT0ERR
Definition: flexcan.hpp:400
constexpr unsigned long CTRL1_SMP
Definition: flexcan.hpp:246
constexpr unsigned long CAN_IFLAG2_25
Definition: flexcan.hpp:503
constexpr unsigned long ECR_RXERRCNT_MASK
Definition: flexcan.hpp:378
constexpr unsigned long CAN_IFLAG1_3
Definition: flexcan.hpp:516
constexpr unsigned long MCR_MAXMB_SHIFT
Definition: flexcan.hpp:208
volatile uint32_t RX14MASK
Definition: flexcan.hpp:141
constexpr unsigned long CRCR_TXCRC_MASK
Definition: flexcan.hpp:589
constexpr unsigned long CTRL2_RFFN_MASK(15U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long MCR_SOFTRST
Definition: flexcan.hpp:230
constexpr unsigned long CTRL1_PRESDIV_SHIFT
Definition: flexcan.hpp:260
constexpr unsigned long RXMGMASK0
Definition: flexcan.hpp:270
constexpr unsigned long MCR_WAKSRC
Definition: flexcan.hpp:224
constexpr unsigned long CAN_IMASK2_20
Definition: flexcan.hpp:428
constexpr unsigned long RXM14MASK7
Definition: flexcan.hpp:312
constexpr unsigned long CAN_IMASK1_17
Definition: flexcan.hpp:460
constexpr unsigned long RXIMR25
Definition: flexcan.hpp:629
constexpr unsigned long CAN_IMASK1_14
Definition: flexcan.hpp:457
constexpr unsigned long CTRL2_RFFN_8MB(0U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long CTRL2_RFFN_112MB(13U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long CAN_IFLAG1_22
Definition: flexcan.hpp:538
constexpr unsigned long CAN_IFLAG2_11
Definition: flexcan.hpp:489
constexpr unsigned long CTRL1_LBUF
Definition: flexcan.hpp:243
constexpr unsigned long RXIMR21
Definition: flexcan.hpp:625
constexpr unsigned long RXIMR18
Definition: flexcan.hpp:622
constexpr unsigned long ESR2_VPS
Definition: flexcan.hpp:581
constexpr unsigned long CAN_IFLAG1_11
Definition: flexcan.hpp:527
constexpr unsigned long CAN_IMASK2_29
Definition: flexcan.hpp:437
constexpr unsigned long MCR_RFEN
Definition: flexcan.hpp:234
constexpr unsigned long CAN_IFLAG2_14
Definition: flexcan.hpp:492
constexpr unsigned long CAN_IFLAG2_10
Definition: flexcan.hpp:488
constexpr unsigned long RXMGMASK7
Definition: flexcan.hpp:277
constexpr unsigned long ESR1_IDLE
Definition: flexcan.hpp:393
constexpr unsigned long MCR_WRNEN
Definition: flexcan.hpp:226
constexpr unsigned long CAN_IMASK2_18
Definition: flexcan.hpp:426
constexpr unsigned long CAN_IMASK1_15
Definition: flexcan.hpp:458
constexpr unsigned long MCR_HALT
Definition: flexcan.hpp:233
constexpr unsigned long RXMGMASK4
Definition: flexcan.hpp:274
constexpr unsigned long CTRL2_RRS
Definition: flexcan.hpp:553
constexpr unsigned long MCR_LPMACK
Definition: flexcan.hpp:225
constexpr unsigned long RXIMR26
Definition: flexcan.hpp:630
constexpr unsigned long CTRL2_RFFN_128MB(15U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long RXM15MASK26
Definition: flexcan.hpp:366
constexpr unsigned long RXM14MASK25
Definition: flexcan.hpp:330
constexpr unsigned long CAN_IMASK2_8
Definition: flexcan.hpp:416
constexpr unsigned long RXM15MASK21
Definition: flexcan.hpp:361
constexpr unsigned long CAN_IFLAG1_28
Definition: flexcan.hpp:544
constexpr unsigned long CTRL1_CLKSRC
Definition: flexcan.hpp:251
constexpr unsigned long CAN_FIFO_OV
Definition: flexcan.hpp:523
constexpr unsigned long CTRL2_EACEN
Definition: flexcan.hpp:551
constexpr unsigned long RXIMR4
Definition: flexcan.hpp:608
constexpr unsigned long CAN_IMASK2_11
Definition: flexcan.hpp:419
constexpr unsigned long CAN_IMASK2_30
Definition: flexcan.hpp:438
constexpr unsigned long RXMGMASK25
Definition: flexcan.hpp:295
constexpr unsigned long ESR1_FLTCONF_MASK
Definition: flexcan.hpp:388
constexpr unsigned long MCR_SLFWAK
Definition: flexcan.hpp:227
constexpr unsigned long RXM15MASK8
Definition: flexcan.hpp:348
constexpr unsigned long ESR2_LPTM_SHIFT
Definition: flexcan.hpp:583
constexpr unsigned long ESR1_FLTCONF_SHIFT
Definition: flexcan.hpp:387
constexpr unsigned long CAN_IFLAG2_1
Definition: flexcan.hpp:479
constexpr unsigned long CAN_IFLAG1_26
Definition: flexcan.hpp:542
constexpr unsigned long RXM14MASK10
Definition: flexcan.hpp:315
constexpr unsigned long CTRL1_PRESDIV_MASK
Definition: flexcan.hpp:261
constexpr unsigned long RXM14MASK1
Definition: flexcan.hpp:306
constexpr unsigned long CAN_IMASK1_13
Definition: flexcan.hpp:456
constexpr unsigned long CAN_IFLAG1_9
Definition: flexcan.hpp:525
constexpr unsigned long CAN_IMASK1_25
Definition: flexcan.hpp:468
constexpr unsigned long CAN_IMASK2_10
Definition: flexcan.hpp:418
constexpr unsigned long TIMER_SHIFT
Definition: flexcan.hpp:265
constexpr unsigned long RXIMR12
Definition: flexcan.hpp:616
constexpr unsigned long CAN_IMASK1_5
Definition: flexcan.hpp:448
constexpr unsigned long RXM15MASK18
Definition: flexcan.hpp:358
constexpr unsigned long RXM14MASK29
Definition: flexcan.hpp:334
constexpr unsigned long CAN_IFLAG1_27
Definition: flexcan.hpp:543
constexpr unsigned long CTRL2_RFFN_80MB(9U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long CTRL2_RFFN_40MB(4U<< CTRL2_RFFN_SHIFT)
constexpr unsigned long CAN_IMASK1_16
Definition: flexcan.hpp:459